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AutodiagHW-1

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The standards relating to the functional safety of machines and electronically managed systems, identify a particular type of test; the diagnostic tests, which are designed to detect faults of the electronic components. Early detection of faults, especially if dangerous, is crucial to keep the system or the machine to a safe state, even in the face of severe abnormalities; In fact the level of safety integrity (SIL) depends strongly on the degree of diagnostic coverage and the percentage of dangerous faults detected.

HINTSW -T & T Systems is able to conceive, plan, design and validate the HW diagnostic test under the requirements of general standards and related to the functional safety. HINTSW -T & T Systems also has the know-how needed to carry out analyzes and calculations designed to determine the frequency of the tests, the percentage of diagnostic coverage and the fraction of detected dangerous failures that contribute to determining the SIL (Safety Integrity Level ) of a system / subsystem / equipment or safety function.


Detailed information

The HW diagnostic tests can be split into two distinct categories:

  • Off-line diagnostic test. This category of test is performed during planned periodic maintenance and can also be performed during any extraordinary maintenance: The tests are usually performed by placing the system or the machine in a particular state of operation, usually called maintenance (or off-line); this state must be specifically provided for this purpose in the design and implementation of the system or machine.
  • Self-diagnosis tests performed in the normal execution time (run-time). This test category is usually performed at start-up and then periodically or continuously is performed (monitoring) during the normal operating state (in operation) of the system or machine; It is the main method of self-diagnosis and allows early detection of possible failures with the consequent early securing of the system or machine.

The diagnostic tests and self-diagnosis, by their nature, it is convenient that they are designed already during the safety analysis (for example the hazard analysis) and, subsequently, they should be designed in detail together with the electronics design the system or machine.

Often the standards require that the design of this type of test also includes the definition of the test execution frequency and the calculation of the fraction of dangerous failures detected and the obtained diagnostic coverage percentage.
The requirements for this type of testing should also be part of the specification of the system security requirements or machine, and should be subjected to the same validation process wich are submitted to all other security requirements of the machine or system.

 

In particular HINTSW - T & T Systems has extensive experience in the design of diagnostic tests as described in the table below ...

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Component Element Test typeTest methodFailure/ Error  detected
Table 1 Main techniques used for diagnostic testing of HW components
CPU Registers Periodic self-test Static memory Glued to
CPU Registers Periodic self-test 

Walkpat; Trasparent Galpat

DC failure
CPU Istructions Periodic self-test Equivalence class Execution and/or   decoding incorrect
CPU Program counter Monitoring Indipendent watchdog timer   Glued to
CPU Program counter Monitoring Indipendent watchdog timer and program sequence control  DC failure
CPU Addressing Periodic self-test Test pattern of the address lines DC failure
CPU Data path instruction

Periodic self-test

Test pattern

DC fault and/or incorrect execution
CPU Data path instruction

Monitoring

Data redundancy

DC fault and/or incorrect execution
Interrupt Excecution and management

Monitoring

Indipendent watchdog timer and program sequence control 

Loss interrupt or interrupt frequency too high
Clock Frequency

Monitoring

Watchdog timer

Wrong frequency
Memories ROM

Periodic self-test

Checksum; CRC (Cyclic Redundancy Check)

Single-bit error, the multi-bit error
Memories ROM

Monitoring

Protection of words with a single parity bit

Single-bit error
Memories RAM

Periodic self-test

Walkpat; Trasparent Galpat DC fault and cross dynamic links
Memories RAM

Monitoring

Protection of words with a single parity bit

DC failure
Memories Addressing

Monitoring

Protection of words including the address with single parity bit

Glued to
Memories Addressing

Monitoring

Protection of words including the address with multiple parity bits

DC failure
Memories Addressin

Periodic self-test

CRC (Cyclic Redundancy Check); Test pattern

DC failure
  Internal data path Data

Monitoring

Protection of words including the address with multiple parity bits. Data redundancy; Protocol test.

Glued to; DC failure
 Internal data path Data

Periodic self-test

Test pattern

Glued to; DC failure
 Internal data path Addressing

Monitoring

Protection of words including the address with multiple parity bits

Glued to; DC failure
 Internal data path Addressing

Periodic self-test

Test patterns including the address

Glued to; DC failure
  External communication Data

Monitoring

Protection of words with multiple parity bits; CRC (Cyclic Redundancy Check); Testing protocol; Transmission redundancy

Hamming distance up to 4
 External communication Addressing

Monitoring

Protection of words including the address with multiple parity bits; CRC (Cyclic Redundancy Check) incuso the address; Testing protocol; Transmission redundancy

Hamming distance up to 4
 External communication Timing Monitoring Scheduled transmission; Monitoring time slot and logical; logical monitoring of the sequence Untimely transmission
 External communication Timing Monitoring Scheduled transmission; Monitoring time slot and logical; logical monitoring of the sequence Wrong sequence
I/O devices Digital I/O Periodic self-test Test pattern Incorrectly input value read;   output value incorrectly set
I/O devices Digital I/O Monitoring Plausibility check; Comparison of the inputs; Multiple parallel outputs; Check the outputs; Incorrectly input value read;   output value incorrectly set
I/O devices  A/D e D/A converters Periodic self-test Test pattern Incorrectly input value read;   output value incorrectly set
I/O devices  A/D e D/A converters Monitoraggio Plausibility check; Comparison of the inputs; Multiple parallel outputs; Check the outputs; Incorrectly input value read;   output value incorrectly set
I/O devices Anologic multiplexer   Periodic self-test Test pattern Wrong addressing
I/O devices Analogic multiplexer   Monitoring Plausibility check; Input Comparison Wrong addressing
Control devices and comparators In this phase begins the coding, or the implementation of the modules. Periodic self-test Control test All outputs do not comply with the static and dynamic functional specifications
Chip custom (ASIC, GAL, ecc.) Chip custom Periodic self-test Periodic self-test and control All outputs do not comply with the static and dynamic functional specifications

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